Historia del Reset Glitch Hack

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Contenido

Historial de versiones

Versión Fecha Autor Placas Kernels Timings Xell Xebuild
1.0 2011-08-28 Gligli Zephyr Jasper Trinity 14699 No_Refurbisheds XC2C64A +Source Build.py no
1.1 2011-09-23 Gligli Falcon 14699 No_Refurbisheds XC2C64A +Source Build.py no
1.1 2011-11-11 TeamXecuter Opus 14699 No_Refurbisheds XC2C64A Build.py no
Trinity 14717/9 2012-03-05 Vola, Marchisio80 Trinity 14717/9 no Build.py no
Trinity 14717/9 2012-03-05 TeamXecuter Trinity 14717/9 no J-Runner265 ?
Xenon 2012-03-07 TeamXecuter Xenon 14699 XC2C64A J-Runner Build.py no
2.0 2012-04-15 TeamSquirt Zephyr Falcon/Opus Jasper 14717/9 y_Refurbisheds Squirt1.2BGA(black) Build.py no
2.0 2012-04-15 TeamXecuter Zephyr Falcon/Opus Jasper 14717/9 y_Refurbisheds XC2C64A Build.py Parches
2.0 2012-04-20 TeamSquirt Zephyr Falcon/Opus Jasper 14717/9 y_Refurbisheds XC2C64A no no
Corona 2012-07-04 TeamSquirt, AutoGG Corona 14717/9 SquirtCorona +Source AutoGG0.6beta Parches
Corona 2012-07-05 TeamXecuter Corona 14717/9 XC2C64A +Source no no

Hacks en placas y kernels

Kernel Fecha Notas Xenon Zephyr Falcon Opus Jasper Trinity Corona v1 Corona v2 Corona v3
1888-14699 (2011-12-06) Fats:CBa Slims:CBa-CBb RGH Xenon (Solo Xell) RGH1 RGH1 RGH1 RGH1 RGH Trinity RGH Corona RGH Corona no
14717-14719 (2012-02-16) Fats:CBa-CBb Slims:CBa-CBb no RGH2 RGH2 RGH2 RGH2 RGH Trinity RGH Corona RGH Corona no
15572-15574 (2012-06-12) Agregado Salt al proceso de cifrado no no no no no no no no no

Puntos en placas y chips

CMod

TXCR

9

F

10

E

40

D

30

C

17

B

13

A

21

GND

20

3V3

Lugar Arriba Arriba Debajo Debajo Arriba Debajo Arriba Arriba
Xenon no no CPU_RST_V1P1_N (C7R112 left pad) POST_OUT1 (FT6U7) STBY_CLK (48Mhz) (C3B2 right pad (ANA)) CPU_PLL_BYPASS (under R7R17) GND (GROUND) (video_connector (AV_PORT)) V_3P3STBY (3.3 Volts) (J2B1_pin7)
Fats RGH1 no no CPU_RST_V1P1_N (J8C1_pin2) POST_OUT1 (FT6U7) STBY_CLK (48Mhz) (C3B2 right pad (HANA)) CPU_PLL_BYPASS (under R7R17) GND (GROUND) (video_connector (AV_PORT)) V_3P3STBY (3.3 Volts) (J2B1_pin7)
Fats RGH2 i2C_SDA (J2B1_pin9) i2C_SCL (J2B1_pin10) CPU_RST (J8C1_pin2) POST_OUT1 (FT6U7) STBY_CLK (48Mhz) (C3B2 right pad (HANA)) no GND (GROUND) (AV_PORT) V_3P3STBY (3.3 Volts) (J2B1_pin7)
Trinity i2C_SDA (J2C3_pin9) i2C_SCL (J2C3_pin10) CPU_RST (FT4R2, near X-Clamp) POST_OUT1 (FT5R2, near X-Clamp) STBY_CLK (48Mhz) (right of C3B10 (HANA)) no GND (GROUND) (Video_connector_shell (AV_PORT)) V_3P3STBY (3.3 Volts) (J2C3_pin7)

Características del CPLD de los chips

Chip Fabricante Tipo G° de velocidad N° de Pins Rango de Temperatura Espacio Pin/Ball °JA (°C/Watt) °JC ({C/Watt) Empaque Dimensiones I/O
X360glitchipv2.1 /tx-coolrunner /Matrix-glitcher /maximus-stinger /x360glitch /c-mod Xilinx xc2c64a-vq44 -7 44 C 0.8mm 46.6 8.2 Very Thin Quad FlatPack; Pb-free 10mm x 10mm 33
360 SQUIRT BGA 1.2 Xilinx xc2c64a-cp56 -7 56 C 0.5mm 65.0 15.0 Chip Scale Package; Pb-free 6mm x 6mm 45